FPGA • ADC • Camera Data Manipulation • USB Interface
Project Overview
The BetterBots project is a robot designed to teach coding and engineering concepts. The task assigned to the Senior Design team at Iowa State is to develop the FPGA portion of the robot. To do this we are utilizing a ECPIX-5 for taking in multiple types of input devices applying logic and outputting the data to another device such as a Raspberry Pi. This includes an FPGA RISC-v core, Camera subsystem, Fast Fourier Transform, and USB stack. The project involved two main fields of development, digital design with a Lattice FPGA and analog circuitry and PCB design. The team split into two groups to handle each aspect of the project. The FPGA portion involved setting up a system with a processor, camera subsystem, and ADC to be accessible for a Raspberry Pi to control and receive information from. USB was used for high-speed communication between the Raspberry Pi and the Risc-V core. The camera subsystem's scope was reduced to writing a set stream of information into memory, and the ADC portion involved reducing noise from the comparator inside the FPGA and improving accuracy and resolution. A pipelined averaging circuit and a wishbone interface were developed to communicate the results of the ADC back to the system. Seen below is a block diagram for this project.
Executive Summary
Development Standards & Practices Used
- IEEE Standard VHDL Language synthesized through Python
- IEEE Standard for Verilog synthesized through Python
Summary of Requirements
- ECPIX-5 FPGA core interface with the USB stack
- Create a development environment for interfacing with ECPIX-5 FPGA core
- Create a camera subsystem for interacting with Camera sensor (OV9732) ECPIX-5 FPGA core
- Create a block in LiteX for connecting ADC to SOC
- Develop off-board Analog-Digital Converter
Applicable Courses from Iowa State University Curriculum
- CPRE 281/288/381/480
- EE 201/230/330/333
New Skills/Knowledge acquired that was not taught in courses.
- Benefits and challenges of using USB based communication.
- VHDL generator frameworks called LiteX
- JTAG
- Serial Communication
Team Members
Raj Singh
Management FPGA Infrastructure ADC Board Design
Jordan McGhee
FPGA Design FPGA Implementation FPGA-ADC Integration
Tyler Smith
ADC Circuit Analysis ADC Circuit Design ADC Board Design
Weekly Reports
Report 1Report 2
Report 3
Report 4
Report 5